This invention relates to programmable logic devices (“PLDs”) such as those that are frequently referred to as field-programmable gate arrays (“FPGAs”). More particularly, the invention relates to the provision of memory circuitry in an FPGA that the user of the FPGA can use as random access memory (“RAM”) during normal logic operation of the device. Still more particularly, the invention relates to selectively employing the circuitry of look-up tables (“LUTs”) on the device that are not needed for normal LUT-based logic to provide the above-mentioned user-accessible RAM. Such RAM may be referred to as “distributed RAM” because, rather than being in a block of dedicated user RAM circuitry, it is distributed over the circuitry of several LUTs on the device.
Lewis et al. U.S. Pat. No. 7,084,665 shows improved circuitry for providing distributed RAM in FPGAs. (The Lewis et al. reference is hereby incorporated by reference herein in its entirety.) For example, the Lewis et al. reference shows sharing a single write decoder by several logic elements (“LEs”), each of which includes a LUT, on an FPGA to reduce the amount of write address circuitry that must be added to give the FPGA distributed user RAM mode capability.
Various extensions or additions to circuitry of the general type shown in the Lewis et al. reference would be helpful in many situations. For example, users often want a synchronous write so that the user does not need to provide exact timing signals for the write strobe. This necessitates provision of a write address and a write data register, but it would be desirable to avoid having to provide dedicated hardware (circuitry) for this function.
Another example of a possibly helpful extension of or addition to what is shown in the Lewis et al. reference would be application of those principles to LEs that are “fracturable” to implement a range of logic function sizes such as one six-input LUT-based logic function or two five-input LUT-based logic functions.
Still another example of a respect in which it could be helpful to extend or add to what is shown in the Lewis et al. reference relates to supporting a synchronous read function. Again, users often prefer a synchronous read, but it would be desirable to avoid having to construct dedicated hardware to support the read address register.